There is a digital modulation technology useful for improvement of high quality transmission and frequency utilizing efficiency available for systems for transmitting video signals and/or audio signals and has been so far used in the fields of microwave ground communications and business use satellite communications. As the digital modulation system, 16QPAM (16-points Quadrature Amplitude Modulation) and 64QPAM (64-points Quadrature Amplitude Modulation), which have a good frequency utilization efficiency, are used for ground microwave telecommunication circuits, etc. On the other hand, a BPSK (Bi-Phase Shift Keying) modulation system and a QPSK (Quadrature Phase Shift Keying) modulation system, etc. which have a relatively low transmission code error rate have been generally used for satellite telecommunication circuits.
FIG. 1 is a block diagram showing a conventional demodulator. A QPSK modulated signal input to an input terminal 1 is parallelly supplied to both an in-phase detector 2 and a quadrature-phase detector 3. Local oscillation signals given to the detectors 2 and 3 are local oscillation signals generated from a fixed frequency local oscillator 5, which are divided to a 0.degree. phase local oscillation signal and a 90.degree. phase local oscillation signal by a distributor 4. Signals detected by the detectors 2, 3 are supplied to A/D converters 6, 7, respectively for conversions into digital values. These digitized detection signals are supplied to digital low-pass filters (LPFs) 8, 9 which have the same frequency transmission characteristic, respectively, for shaping their spectrums. These digital LPFs 8, 9 provide transmission characteristics required for preventing intersymbol interferences in a digital data transmission. These digital LPFs 8, 9 are also designed so that so-called roll off characteristics can be generally obtained when then are associated with filter characteristics in transmission part. Therefore, the detection signals are spectrally shaped through these digital LPFs 8, 9 to make the eye-aperture rate sufficiency large. These filtered signals from the digital LPFs 8, 9 are each branched into two paths so that ones are supplied to a clock regenerator 10 where symbol timing component in the signal is extracted and fed back to the conversion clock inputs of the A/D converters 6 and 7. While the other signals branched from the digital LPFs 8, 9 are supplied to a complex multiplier 11.
The complex multiplier 11 operates in an almost similar manner as a conventional frequency converter, i.e., a mixer for converting a high frequency signal into a constant intermediate frequency signal. Here it is noted that a real number type multiplier using no complex number is able to perform the detecting operation but not able to operate as a general frequency converter since it fails to express negative frequency components. The multiplexed signal output from the complex multiplier 11 is input to a phase comparator 12 where a phase difference between the multiplexed signal and an oscillation signal generated by a numerical controlled oscillator (NCO), that will be described later, is detected. The output (phase difference information) of the phase comparator 12 is input to a data discriminator 13. The data discriminator 13 discriminates QPSK data, that is, demodulate it from the phase difference information and outputs the demodulated data.
Further, this phase difference information from the phase comparator 12 is input to the frequency control terminal of a NCO 15 via a loop filter 14 for regenerating carrier. The NCO 15 is a cumulative adder that does not prohibit overflow and according to a signal value input to the frequency control terminal, performs the adding operation up to its dynamic range and therefore, is placed in the oscillating state and its oscillation frequency changes according to a control signal value. That is, it operates in the entirely same manner as a voltage controlled oscillator (VCO) in an analog circuit. What are differing from a general VCO are that its oscillation frequency is extremely stable and it has a stability more than a so-called VCO (VCXO) using a crystal and a wide frequency variable range that cannot be realized by VCXO. The output of the NCO 15 is branched into two paths which return to the complex multiplier 11 via data converters 18, 17 having sine and cosine characteristics, respectively. This feedback loop from the the loop filter 14 to the complex multiplier 11 constitutes a PLL having a full digital construction in cooperation with the phase comparator 12. Here it is assumed that if the loop filter 14 includes a full integration system, the frequency pull-in range of the PLL is infinite as a principle and an ideal PLL operation can be expected.
Further, the circuits after the A/D converters 6, 7 are all for digital signal processing and when integrated, a demodulator, which is a very compact device, can be realized without any adjustment.
Next, an AFC loop has been formed in this system. That is, the phase difference signal output from the phase comparator 12 is supplied to a frequency error detector 19. This frequency error detector 19 detects a frequency error between an input and a local oscillation signal. This frequency error component is smoothed by an AFC loop filter 20 and supplied to the frequency control terminal of an NCO 22 via a latch 21. The NCO 22 oscillates a sawtooth waveform signal and then supplies the oscillation signal to a data converter 24 having a sine or cosine conversion characteristic. The output of the data converter 24 is supplied to a D/A converter 25 where the oscillation signal is converted into a corresponding analog signal. The D/A converter 25 supplies the oscillation signal to a phase detector 26 which comprises a frequency multiplier in cooperation with an amplifier 27, an oscillator 28 and a frequency divider 29. The frequency multiplier supplies the frequency multiplied signal to the distributor 4 wherein the signal is divided into the 90.degree. local oscillation signal and the 0.degree. local oscillation signal as described previously.
When the frequency retuning is made sufficiently small by the AFC operation, the frequency error detection output of the frequency error detector 19 varies. As a result, a loop switching signal is output from the frequency error detector 19 and at the same time, an AFC hold signal is output. These two signals are substantially the same. The loop switching signal switches the loop filter 14 in the PLL to the operating state. Thus, the PLL operation starts and the frequency error information in the AFC loop is held when the AFC is in the best state. The PLL starts the frequency pull-in operation to synchronize with carrier.
Next, a frequency multiplier in the fixed frequency local oscillator 5 will be explained.
The frequency multiplier comprises the phase detector 26, the amplifier 27 which amplifies the detection output of the phase detector 26, the VCO 28 to which frequency control terminal the output of the amplifier 27 is supplied, and the frequency divider 29 which makes N-division of the output of the VCO 28. The output of the frequency divider 29 is supplied to the phase detector 26. This circuit comprises the PLL. For instance, if the output of the D/A converter 25 is 4.375 MHz and a dividing ratio of the frequency divider 29 is 32, oscillation frequency of the VCO 28 becomes 140 MHz. Further, to make oscillation frequency of the NCO 22 to 4.275 MHz in the state without frequency errors, it is only needed to add an offset equivalent to this oscillation frequency to the frequency control input of the NCO 22 in advance.
As a result, it is possible to regard the circuit ranging from the NCO 22 to the VCO 28 as a single 140 MHz NCO. Therefore, this oscillation frequency is extremely stable and it is possible to get the stability of several ten times of the ordinary stability of the VCO 28.
Further, the amplifier 27 contained in the frequency multiplier is normally a loop filter. In this case, however, if the response of the frequency multiplier is made as fast as possible, there is an advantage to facilitate design of the entire AFC loop. Therefore, the amplifier 27 is not shown as a loop filter but is simply shown as an amplifier (if the response of the frequency multiplier is slow, this time constant is decided by the overall characteristic of the time constant of the AFC loop filter). The output of the VCO 28 is input to the 0.degree. and 90.degree. distributor 4 and is turned to the in-phase detected local oscillation signal and the D-A detected local oscillation signal, respectively.
Since local oscillation signals are fed back and controlled by the frequency error signal, they are D-A synchronous detected in the state almost without frequency detuning. Therefore, when shaped the spectrums, they can be demodulated in the almost ideal state without the spectrum being narrowed.
Further, as a large delay element is not contained in the carrier regeneration PLL as described above, it is possible to regenerate carrier with a good jitter characteristic. Further, as the wide PLL frequency pull-in range is available, an extremely severe characteristic is not required for the AFC operation. That is, even when some frequency error in the pull-in range of this PLL circuit remains, it is possible to regenerate the carrier.
FIG. 2A is a definite example of the NCO 22 for the AFC loop. The substance of the NCO 22 is the same as the NCO 15 in the PLL. A signal input to a frequency control terminal 200 is supplied to the one of the inputs of an adder 201 and the output of the adder 201 is supplied to the other input after delayed by one clock by a latch 202. As a result, the latch 202 acts as an accumulator for generating a sawtooth wave signal. The frequency of the sawtooth wave signal is controllable by a numerical value applied to the control terminal 200 if a clock has a fixed frequency.
FIG. 2B is an exemplified arrangement of the frequency error detector 19 in the embodiment described above. It is assumed that a phase difference signal is supplied to an input terminal 300. The circuit comprising a latch 301 using symbol timing of the digital modulated signal as a clock and a subtractor 302 detects a phase difference between symbols of the digital modulated signals. This is nothing but to detect a frequency error. Therefore, this phase difference signal is supplied to an output terminal 303. Further, the frequency error detection output is also branched to an LPF 304 and after smoothed sufficiently by this filter, binalized in a binarizer 308 via an absolute value circuit 305 which removes plus and minus symbols. This binarized output is transmitted as a signal to select whether AFC or PLL operation is to be executed (the former AFC hold and loop switching signal).
The prior art AFC circuit for the QPSK demodulator, as described above, has a problem of frequency pull-in range. As this AFC circuit detects the frequency error through a detection of a phase difference between symbols, the AFC circuit can detect the frequency error up to .+-.1/8 of a symbol rate of a QPSK modulated signal. Therefore, the frequency pull-in range of the AFC circuit is limited to the range of .+-.1/8 of the symbol rate of QPSK modulated signal, so that the AFC circuit cannot cope with a frequency error exceeding the range.